Implementation of JPEG2000 Arithmetic Decoder using Dynamic Reconfiguration of FPGA (WA-P6)

Author(s) : Sophie Bouchoux (LE2I, France) Elbay Bourennane (LE2I, France) Michel Paindavoine (LE2I, France)

Abstract : This paper describes the implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board by using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance, logic cost,spatio-temporal efficiency) have been defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation based on four partial configurations of arithmetic decoder allows reducing significantly the number of logic cells (57%) in comparison with static implementation.

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