Design flexibility using FPGA dynamical reconfiguration (WA-P6)

Author(s) : Nicolas Abel (ETIS - UMR 8051 CNRS, France) Lounis Kessal (ETIS - UMR 8051 CNRS, France) Didier Demigny (ETIS - UMR 8051 CNRS, France)

Abstract : In this paper, we detail the implementation of an image processing algorithm on the dynamically reconfigurable architecture ARDOISE. Beyond the complexity of this algorithm, we pay our attention on the possibilities offered by dynamic reconfiguration paradigm. We insist particularly on the software management of reconfigurations and on the flexibility it leads. We spread these concepts, tested practically on ARDOISE, in more complex cases which will be the object of future studies.

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