Improved Throughput Arithmetic Coder for JPEG2000 (WA-P6)

Author(s) : Michael Dyer (University of New South Wales, Australia) David Taubman (University of New South Wales, Australia) Saeid Nooshabadi (University of New South Wales, Australia)

Abstract : Increasing the throughput of the JPEG2000 block coder requires bit-plane and arithmetic coders capable of concurrent symbol processing. Previously described MQ coders are capable of consuming 1 symbol or less per clock cycle. We develop a new arithmetic coder that can process exactly two symbols per clock cycle. The technique is implemented on a FPGA, and is compared with our previous "Hypothesis Testing" arithmetic coder and a reference one symbol per cycle coder. Our implementation gives an increase in throughput of 1.9 times, at the cost of 1.7 times as much hardware, when compared to the reference coder. It also has 1.2 times the throughput, while consuming only 70% of the hardware associated with the Hypothesis Testing coder.

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